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[DPRG] V4L capture loop timing constraints
Subject: [DPRG] V4L capture loop timing constraints
From: Ed Okerson
ed at okerson.com
Date: Fri Jun 1 09:56:12 CDT 2007
Chris,
> My experience with this using the Michael Xhaard spca5xx driver
> on a 200 MHz ARM9 PC104 SBC is tight timing constraints between
> ioctl calls. In my application (Stella the robot), frame
> processing must be between 70 to 80 ms or else most captured
> images are corrupted. Unfortunately, I am stuck with a 2.4.x
> kernel so can not provide timing resolution better than 10 ms
> granularity.
You can increase the frequency of the timer tick on 2.4.x and earlier
kernels, it just requires a kernel re-compile. I don't have a 2.4 kernel
around anymore, but if you grep for HZ in the kernel source you will find
that it is currently defined as 100, which means the main timer ticks at
100Hz, if you change that value to 1000 and recompile your kernel, you
will now have 1 ms granularity.
Ed Okerson
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